The present invention relates to a semiconductor device and, more particularly, to a semiconductor chip package in which a semiconductor chip is electrically connected to a substrate by wire bonding. Generally, in forming such a package, a semiconductor chip is attached to a mounting means such as a substrate or lead frame using a liquid adhesive.
FIG. 1 is a cross-sectional view showing an example of a conventional semiconductor chip package assembled with a liquid adhesive. FIG. 2 is a cross-sectional view showing another example of a conventional semiconductor chip package assembled with a liquid adhesive.
As illustrated in FIG. 1, a semiconductor chip package 310 includes a single semiconductor chip 311. The semiconductor chip 311 is attached to a printed circuit board 321 by a layer of liquid adhesive 325. Chip pads 312 are connected to substrate pads 322 by bonding wires 327.
As illustrated in FIG. 2, a semiconductor chip package 410 includes two semiconductor chips in a vertical stack. A first semiconductor chip 411 is attached to a printed circuit board 421 using a layer of liquid adhesive 425. A second semiconductor chip 413 is then attached to the first semiconductor chip 411 by a layer of liquid adhesive 426. Chip pads 412 and 414 and the semiconductor chips are electrically connected to substrate pads 422 by bonding wires 427.
The semiconductor chip packages 310 and 410 are commonly protected from external environments by sealing portions 335 and 435, respectively. The sealing portions 335 and 435 are typically made of an epoxy molding compound (EMC). The sealing portions 335 and 435 seal the semiconductor chips 311, 411 and 413, the bonding wires 327 and 427, and the connection portions of the semiconductor chips and bonding wires. Solder balls 337 and 437 are attached on the bottom surface of the printed circuit boards 321 and 421 and function as external connection terminals.
In the conventional semiconductor chip packages illustrated in FIGS. 1 and 2, the semiconductor chips are attached using a liquid adhesive. The use of liquid adhesive in assembling chip packages may introduce processing complications including the need to maintain a uniform quantity of adhesive to reduce voids under the chip and to reduce adhesive overflows onto the semiconductor chip and substrate. The presence of such defects may degrade the reliability of the final semiconductor product. Further, when a semiconductor chip package is produced by vertically stacking a plurality of semiconductor chips, the liquid adhesive may contaminate the semiconductor chip pads and possibly complicate or degrade the performance of subsequent processes or the reliability of the resulting semiconductor device.
In an effort to address some of the problems associated with liquid adhesives, film-type non-conductive adhesive tape has been used to replace liquid adhesive for mounting semiconductor chips. FIG. 3 is a cross-sectional view of an example of a conventional semiconductor chip package using an adhesive tape for mounting the semiconductor chip.
As illustrated in FIG. 3, a semiconductor chip package 510 includes two semiconductor chips 511 and 513 provided in a vertical stack. A first semiconductor chip 511 is attached to a printed circuit board 521 by a liquid adhesive layer 525. A second semiconductor chip 513 is attached to the first semiconductor chip 511 by a non-conductive adhesive tape 526. The adhesive tape 526 is sized to be located generally within chip pads 512 of the first semiconductor chip 511, and with a thickness that provides a space for the wire loop portion of bonding wires 527b connecting the chip pads 512 to substrate pads 522.
In attaching a semiconductor chip using an adhesive tape, however, misalignment may result in the adhesive tape covering a portion of the chip pads or extending beyond the chip edge so that the wires may not be bonded normally to the chip pads. Furthermore, the empty space remaining between the upper chip and the lower chip at their periphery may compromise the process of attaching bonding wires to the upper chip resulting in poor bonds and/or damaged chips and may result in voids in the EMC.